Daniel Grund

About Me

I was born in April 1980 in Karlsruhe, Germany. Form 2000 to 2005 I studied computer science at the University of Karlsruhe spending quite some nice time at the IPD Goos. 2006 I was happy to get PhD scholarship and joined the group of Reinhard Wilhelm at the Saarland University.

Research Interests

Real-Time and Embedded Systems: Timing Analysis, Predictability, Properties of Caches
Compiler Construction: SSA, Register Allocation, Coalescing

Projects

Publications

[1]	Reinhard Wilhelm, Sebastian Altmeyer, Claire Burguière, Daniel Grund, Jörg Herter, Jan Reineke, Björn Wachter, and Stephan Wilhelm. Static timing analysis for hard real-time systems. In VMCAI, pages 3-22. Springer Verlag, 2010. [ bib ]
[2]	Daniel Grund and Jan Reineke. Abstract interpretation of FIFO replacement. In Jens Palsberg and Zhendong Su, editors, Static Analysis, 16th International Symposium, SAS 2009, volume 5673 of LNCS, pages 120-136. Springer-Verlag, August 2009. [ bib \| DOI \| .pdf ]
[3]	Daniel Grund, Jan Reineke, and Gernot Gebhard. Branch target buffers: WCET analysis and timing predictability. In 15th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009, August 2009. [ bib \| .pdf ]
[4]	Reinhard Wilhelm, Daniel Grund, Jan Reineke, Marc Schlickling, Markus Pister, and Christian Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Transactions on CAD of Integrated Circuits and Systems, 28(7):966-978, July 2009. [ bib ]
[5]	Daniel Grund and Jan Reineke. Estimating the performance of cache replacement policies. In MEMOCODE '08: Proceedings of the 6th IEEE/ACM International Conference on Formal Methods and Models for Codesign, pages 101-111, June 2008. [ bib \| .pdf ]
[6]	Jan Reineke and Daniel Grund. Relative competitiveness of cache replacement policies. In SIGMETRICS '08: Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, pages 431-432, New York, NY, USA, June 2008. ACM. [ bib \| DOI \| .pdf ]
[7]	Jan Reineke and Daniel Grund. Relative competitive analysis of cache replacement policies. In LCTES '08: Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems, pages 51-60, New York, NY, USA, June 2008. ACM. [ bib \| DOI \| .pdf ]
[8]	Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont-De-Dinechin, and Fabrice Rastello. Fast liveness checking for SSA-form programs. In CGO '08: Proceedings of the sixth annual IEEE/ACM international symposium on Code generation and optimization, pages 35-44, New York, NY, USA, April 2008. ACM. [ bib \| DOI \| .pdf ]
[9]	Jan Reineke and Daniel Grund. Sensitivity of cache replacement policies. Reports of SFB/TR 14 AVACS 36, SFB/TR 14 AVACS, March 2008. ISSN: 1860-9821, http://www.avacs.org. [ bib \| .pdf ]
[10]	Jan Reineke, Daniel Grund, Christoph Berg, and Reinhard Wilhelm. Timing predictability of cache replacement policies. Real-Time Systems, 37(2):99-122, November 2007. [ bib \| DOI \| .pdf ]
[11]	Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont-De-Dinechin, and Fabrice Rastello. Fast liveness checking for SSA-form programs. Technical Report RR-2007-45, INRIA, November 2007. [ bib \| http ]
[12]	Daniel Grund and Sebastian Hack. A fast cutting-plane algorithm for optimal coalescing. In Shriram Krishnamurthi and Martin Odersky, editors, Compiler Construction - CC 2007, volume 4420 of Lecture Notes In Computer Science, pages 111-115. Springer Verlag, March 2007. Braga, Portugal. [ bib \| .pdf ]
[13]	Rubino Geiß, Veit Batz, Daniel Grund, Sebastian Hack, and Adam M. Szalkowski. GrGen: A fast SPO-based graph rewriting tool. In A. Corradini, H. Ehrig, U. Montanari, L. Ribeiro, and G. Rozenberg, editors, Graph Transformations - ICGT 2006, volume 4178 of Lecture Notes in Computer Science. Springer Verlag, September 2006. Natal, Brasilia. [ bib \| .pdf ]
[14]	Jan Reineke, Daniel Grund, Christoph Berg, and Reinhard Wilhelm. Predictability of cache replacement policies. Reports of SFB/TR 14 AVACS 9, SFB/TR 14 AVACS, September 2006. ISSN: 1860-9821, http://www.avacs.org. [ bib \| .pdf ]
[15]	Sebastian Hack, Daniel Grund, and Gerhard Goos. Register allocation for programs in SSA form. In Andreas Zeller and Alan Mycroft, editors, Compiler Construction - CC 2006, volume 3923 of Lecture Notes In Computer Science. Springer Verlag, March 2006. Vienna, Austria. [ bib \| DOI \| .pdf ]
[16]	Sebastian Hack, Daniel Grund, and Gerhard Goos. Towards register allocation for programs in SSA form. Technical report, University of Karlsruhe, September 2005. [ bib \| .pdf ]
[17]	Daniel Grund. Kopienminimierung in einem SSA-basierten Registerzuteiler. Master's thesis, Universität Karlsruhe, August 2005. [ bib \| .pdf ]
[18]	Daniel Grund. Negative Anwendungsbedingungen für den Graphersetzer GrGen. Studienarbeit, 2004. [ bib ]

Selected Talks

Attended Conferences, Workshops and Seminars

PLDI and LCTES, Tucson, USA, June 2008
MeMoCode, Anaheim, USA, June 2008
CGO 2008 and STMCS, Boston, USA, April 2008
Dagstuhl "zehn plus eins", Dagstuhl, Germany, June 2007
ETAPS 2007, Braga, Portugal, March 2007
ETAPS 2006, Vienna, Austria, March 2006

Miscellaneous

Poster on Relative Competitiveness, June 2008.
Technical Report: Estimating the Performance of Cache Replacement Policies supplementing our Memocode 2008 paper of the same title.
Best Paper Award for "Fast Liveness Checking for SSA-Form Programs" at CGO 2008.
Poster on Timing Predictability, September 2007.
EAPLS Best Paper Award for "A Fast Cutting Plane Algorithm for Optimal Coalescing" at Compiler Construction 2007.
Notes on Optimal Coalescing, January 2007.
Poster on Optimal Coalescing, September 2006.

Supervised Theses

Ongoing thesis: Towards Timing Analysis for Multi-core Systems

Address

Daniel Grund
Universität des Saarlandes
Campus E1 3
D-66123 Saarbrücken

Building E1 3, Room 402
Tel: +49 (681) 302 5571
Fax: +49 (681) 302 3065
Mail:

Compiler Design Lab